As one of the scaling techniques for increasing the density of semiconductor devices, a multi-gate transistor has been suggested. The multi-gate transistor may be obtained by forming a fin- or nanowire-shaped silicon body on a substrate and forming gates on the surface of the silicon body.
The multi-gate transistor can be easily scaled because it uses a three-dimensional (3D) channel. In addition, the current control capability can be improved without the need to increase the gate length of the multi-gate transistor. Moreover, it is possible to effectively suppress a short channel effect (SCE) in which an electric potential of a channel region may be affected by a drain voltage.